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Innovative 2.5D and 3D IC packaging technology dramatically increases bandwidth and performance while also reducing power and cost of high-performance ASIC designs.
Separating typically single homogeneous, system-on-chip (SoC) ASIC device into different, unpackaged ASIC devices (chiplets) continues to gain traction. Function-specific chiplets are interconnected into a single heterogeneous integrated package (IP) with better performance at a reduced cost, higher yield and lower power.
Adoption requires industry standardizations to ensure compatibility between suppliers. Read the proposed set of standardized chiplet model paper by members of the Chiplet Design Exchange (CDX).
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